Subversion Repositories Electronics.Rangefider

* source ISL28113_SPICEmodel
*Model covers the ISL28113, ISL28213 and the ISL28413
* Revision C, LaFontaine October 9th 2009
* Model for Noise, supply currents, CMRR 72dB f=35kHz ,AVOL 85dB f=100Hz
* SR = 1.0V/us, GBWP 2MHz, 2nd pole 3MHz Output voltage clamp and short ckt I limit
*Copyright 2009 by Intersil Corporation
*Refer to data sheet ¡°LICENSE STATEMENT¡± Use of 
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections:          +input
*                       |       -input
*                       |       |       +Vsupply
*                       |       |       |       -Vsupply
*                       |       |       |       |       output
*                       |       |       |       |       |
.subckt ISL28113                Vin+    Vin-    V+      V-      VOUT
* source ISL28113_DS rev1
*
*Voltage Noise
E_En         VIN+ EN 28 0 1
D_D13         29 28 DN
V_V9         29 0 .00035
R_R21         28 0 800E3
*
*Input Stage
M_M14         3 1 5 5  NCHANNELMOSFET
M_M15         4 VIN- 6 6 NCHANNELMOSFET 
M_M16         11 VIN- 9 9 PMOSISIL
M_M17         12 1 10 10 PMOSISIL
I_I1         7 V-- DC 5e-3
I_I2         V++ 8 DC 5e-3
I_IOS         VIN- 1 DC 25e-12 
G_G1A         V++ 14 4 3 1404
G_G2A         V-- 14 11 12 1404
V_V1         V++ 2 1e-6
V_V2         13 V-- 1e-6
R_R1         3 2  1.0004 
R_R2         4 2  1.0004 
R_R3         5 7  10 
R_R4         7 6  10 
R_R5         9 8  10 
R_R6         8 10  10 
R_R7         13 11  1 
R_R8         13 12  1 
R_RA1         14 V++  1  
R_RA2         V-- 14  1 
C_CinDif         VIN- EN  1.02E-12  
C_Cin1         V-- EN  1.26e-12  
C_Cin2         V-- VIN-  1.26e-12  
*
*1st Gain Stage
G_G1         V++ 16 15 VMID 334.753e-3
G_G2         V-- 16 15 VMID 334.753e-3
V_V3         17 16 .61
V_V4         16 18 .61
D_D1         15 VMID DX
D_D2         VMID 15 DX
D_D3         17 V++ DX 
D_D4         V-- 18 DX 
R_R9         15 14  100 
R_R10         15 VMID  1e9 
R_R11         16 V++  1 
R_R12         V-- 16  1 
*
*2nd Gain Stage
G_G3         V++ VG 16 VMID 24.893e-3
G_G4         V-- VG 16 VMID 24.893e-3
V_V5         19 VG .604
V_V6         VG 20 .604
D_D5         19 V++ DX 
D_D6         V-- 20 DX
R_R13         VG V++  318.329e3 
R_R14         V-- VG 318.329e3  
C_C2         VG V++ 5E-09  
C_C3         V-- VG 5E-09  
*
*Mid supply Ref
E_E4         VMID V-- V++ V-- 0.5
E_E2         V++ 0 V+ 0 1
E_E3         V-- 0 V- 0 1
I_ISY         V+ V- DC 90e-6 
*
*Common Mode Gain Stage with Zero
G_G5         V++ VC VCM VMID 2.5118E-10
G_G6         V-- VC VCM VMID 2.5118E-10
E_EOS         1 EN VC VMID 1
R_R15         VC 21  1e6 
R_R16         22 VC  1e6  
R_R22         EN VCM  5e11 
R_R23         VCM VIN-  5e11 
L_L1         21 V++ 4.5474
L_L2         22 V-- 4.5474
*
*Pole Satge
G_G7         V++ 23 VG VMID 188.49e-6
G_G8         V-- 23 VG VMID 188.49e-6
R_R17         23 V++  5305.32 
R_R18         V-- 23 5305.32 
C_C4         23 V++  10e-12   
C_C5         V-- 23  10e-12  
*
*Output Stage with Correction Current Sources
G_G9         26 V-- VOUT 23 0.02 
G_G10         27 V-- 23 VOUT 0.02
G_G11         VOUT V++ V++ 23 0.02
G_G12         V-- VOUT 23 V-- 0.02
V_V7         24 VOUT .08
V_V8         VOUT 25 .08
D_D7         23 24 DX
D_D8         25 23 DX
D_D9         V++ 26 DX
D_D10         V++ 27 DX 
D_D11         V-- 26 DY
D_D12         V-- 27 DY
R_R19         VOUT V++  50 
R_R20         V-- VOUT  50       
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3 vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28113