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* PSpice Model Editor - Version 16.2.0
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*$
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* UCC21220AD
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* (C) Copyright 2017 Texas Instruments Incorporated. All rights reserved.
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*****************************************************************************
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** This model is designed as an aid for customers of Texas Instruments.
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** TI and its licensors and suppliers make no warranties, either expressed
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** or implied, with respect to this model, including the warranties of
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** merchantability or fitness for a particular purpose. The model is
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** provided solely on an "as is" basis. The entire risk as to its quality
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** and performance is with the customer
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*
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* This model is subject to change without notice. Texas Instruments
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* Incorporated is not responsible for updating this model.
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*
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*****************************************************************************
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*
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** Released by: WEBENCH Design Center, Texas Instruments Inc.
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* Part: UCC21220AD
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* Date: 15AUG2018
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* Model Type: TRANSIENT
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* Simulator: PSPICE
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* Simulator Version: 16.2.0.s003
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* EVM Order Number: NA
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* EVM Users Guide: NA
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* Datasheet: SLUSCK0-APRIL 2017-REVISED OCTOBER 2017
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*
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* Model Version: Final 1.00
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*
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*****************************************************************************
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*
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* Updates:
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*
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* Final 1.00
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* Release to Web.
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*
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*****************************************************************************
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*
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* Model Usage Notes:
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*
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* 1. The following features have been modeled
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* a. Switching Characteristics such as propagation delay, rise/fall time
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* b. VCCI UVLO and VDDA/VDDB UVLO turn-on/turn-off propagation delays
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* c. Operating Current v/s VDDA/VDDB, switching frequency and Cload at
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* room temperature
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* d. Deadtime and overlap programming
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* e. Peak output source/sink current
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* 2. This model is for 8V UVLO version
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* 3. Temperature effects have not been modeled.
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* source UCC21220AD_TRANS
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.SUBCKT UCC21220AD_TRANS DISABLE GND INA INB OUTA OUTB VCCI_0 VCCI_1 VDDA VDDB VSSA VSSB NC0 NC1 NC2 NC3
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R_R4 0 INA_OK 1K TC=0,0
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E_ABM6 DRVB 0 VALUE { IF(V(N16672594) > 2.5, V(N16673112), 0) }
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R_R36 N16671640 N16671702 1 TC=0,0
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E_E27 INB_OKD 0 INB_OK 0 1
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C_C38 0 N17110019 2n
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R_R45 N16672776 VDDB 0.5 TC=0,0
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R_R40 INB_OKD N17396123 2 TC=0,0
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E_ABM4 UVLOA 0 VALUE { if ( V(N16670780) > V(N16668898), 5 , 0 ) }
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E_E28 INA_OKD 0 INA_OK 0 1
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E_E9 N17051757 0 VALUE { if ( V(DRVB, 0) <2.45, 5, 0 ) }
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G_ABM2I2 N16671580 N16671552 VALUE { IF(V(INA_OKD) < 2.5 ,
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+ If(V(DEAD_THRESH)< 5u, 0.35, LIMIT((V(DEAD_THRESH)*100/V(VCCI_INT)), 0.35,0)),
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+ 0) }
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T_T1 INA_PRE 0 INA_OK 0 Z0=1K TD=22n
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X_U60 N17110019 N17110021 D_D1
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R_R35 INB_OKD N16670162 3.5 TC=0,0
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R_R1 UVLO1 UVLO1_DELAYED 36k TC=0,0
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C_C35 0 N17396123 1.443n
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R_R43 GND VCCI_0 1G TC=0,0
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E_ABM31 N16669068 0 VALUE { IF( (V(NO_DT)>2.5 |
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+ +V(DRVA_PASS) >2.5) &
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+ +V(N16670790) >2.5, 5, 0) }
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R_R46 UVLO1 N168057010 770 TC=0,0
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X_S4 N17153666 0 N17127259 VSSA UCC21220AD_TRANS_S4
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R_R44 N17051757 N17051744 3.3 TC=0,0
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E_ABM21 INB_PRE 0 VALUE { IF(V(N16673790) > 0.51 , 5 , 0) }
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C_C32 0 N16671702 1n
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E_ABM5 DRVA 0 VALUE { IF(V(N16669068) > 2.5, V(N16669580), 0) }
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C_C29 0 N16671468 1n
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C_C23 0 N16671236 1.443N
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X_U47 INB_OKD N17396123 D_D1
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E_E12 N16673492 N16673432 N16671166 0 {-0.8/5}
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E_E15 N17110038 VSSA N17110019 0 1
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X_U56 UVLO2_DELAYED N168247370 D_D1
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C_C1 0 UVLO1_DELAYED 1.443n TC=0,0
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X_U55 UVLO1_DELAYED N168057010 D_D1
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E_E3 N16669308 OUTA VALUE { if ( V(DRVA, 0) >2.5, 12, 0 ) }
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E_E5 N16668898 N16668890 N17196585 0 {-0.3/5}
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C_C37 0 N17051744 2n
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X_U62 DRVB N17167706 INV_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5
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R_R47 UVLOA N168247370 340 TC=0,0
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R_R42 N16670816 VCCI_0 1 TC=0,0
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R_R53 N17196585 UVLOA 1 TC=0,0
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R_R3 GND INA 50k TC=0,0
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R_R30 N16669868 N16672528 5 TC=0,0
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X_U38 INB_OKD N16670162 D_D1
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E_ABM3 N16673116 0 VALUE { if ( V(INB_INT) > V(N16673418), 1, 0 ) }
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X_U59 N17051744 N17051757 D_D1
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R_R50 N17088411 OUTA 0.135 TC=0,0
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E_E23 N16671044 0 VDDB VSSB 1
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X_M15 N16672968 N17051771 VSSB LOWMOS
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X_U39 INA_OKD N16671830 D_D1
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E_E1 N16669842 N16669834 N17201974 0 {-0.2/5}
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R_R2 UVLOA UVLO2_DELAYED 50k TC=0,0
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R_R48 UVLOB N168409120 340 TC=0,0
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X_S2 N16671850 0 N16671552 0 UCC21220AD_TRANS_S2
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X_U35 OUTB VDDB D_D1
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E_E25 N16673358 0 DISABLE GND 1
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E_ABM24 N16670228 0 VALUE { IF( V(N16670120) > V(N16670672) , 5 , 0 )
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+ }
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V_V3 N16668890 0 5.5
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X_M12 N16970878 N16669308 OUTA HIGHMOS
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C_C28 0 N16670120 1n IC=0
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C_C2 0 UVLO2_DELAYED 1.443n TC=0,0
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X_U57 UVLO2B_DELAYED N168409120 D_D1
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E_ABM29 N16671850 0 VALUE { IF( V(INA_OKD)<2.5 &
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+ +V(N16671830) >2.5, 5, 0 ) }
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E_E14 N17051771 VSSB N17051744 0 1
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E_E19 INA_INT 0 INA GND 1
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V_V1 N16669834 0 2.7
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C_C40 VSSB N17167704 110p
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C_C33 0 N16671552 1n IC=0
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T_T3 N16671236 0 N16669674 0 Z0=1K TD=19n
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R_R51 N16672968 OUTB 0.135 TC=0,0
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R_R55 N17201974 UVLO1 1 TC=0,0
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V_V4 N16673354 0 1.8
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R_R6 UVLOB UVLO2B_DELAYED 50k TC=0,0
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X_U42 UVLOA FAULT_INP N16670790 AND2_BASIC_GEN PARAMS: VDD=5 VSS=0
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+ VTHRESH=2.5
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E_E21 VCCI_INT 0 VCCI_0 GND 1
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E_E2 N16672306 N16672276 N16669868 0 {-0.8}
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C_C43 0 N17201974 1n
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E_E24 DIS 0 N16669674 0 1
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X_U40 N16671552 N16671580 D_D1
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X_S1 N16670408 0 N16670120 0 UCC21220AD_TRANS_S1
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C_C3 0 UVLO2B_DELAYED 1.443n TC=0,0
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X_U44 UVLO1 N16698404 FAULT_INP AND2_BASIC_GEN PARAMS: VDD=5 VSS=0
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+ VTHRESH=2.5
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E_ABM8 N16671166 0 VALUE { if ( V(N16673358) > V(N16673492), 5 , 0 )
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+ }
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I_IQuiescentA VDDA VSSA DC 1.2m
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X_S3 DRVA 0 VDDA N17127259 UCC21220AD_TRANS_S3
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E_ABM2 N16669868 0 VALUE { if ( V(INA_INT) > V(N16672306), 1 , 0 ) }
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X_U37 N16670120 N16670154 D_D1
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R_R56 INA_OKD N17407797 2 TC=0,0
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E_E4 N17110021 0 VALUE { if ( V(DRVA, 0) <2.45, 5, 0 ) }
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E_E8 N16673112 0 INB_OK 0 1
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I_Iq_vcc VCCI_0 GND DC 2m
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E_E22 N16670780 0 VDDA VSSA 1
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E_ABM7 UVLOB 0 VALUE { if ( V(N16671044) > V(N16670896), 5 , 0 ) }
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E_ABM32 N16672594 0 VALUE { IF( (V(NO_DT)>2.5 |
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+ +V(DRVB_PASS) >2.5) &
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+ +V(N16669858) >2.5, 5, 0) }
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X_S5 DRVB 0 VDDB N17167704 UCC21220AD_TRANS_S5
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X_M13 N17088411 N17110038 VSSA LOWMOS
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E_ABM20 INA_PRE 0 VALUE { IF(V(N16672528) > 0.51 , 5 , 0) }
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E_ABM25 NO_DT 0 VALUE { IF(V(DEAD_THRESH) <1n, 5,0) }
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X_U48 INA_OKD N17407797 D_D1
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V_V2 N16672276 0 1.8
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R_R49 N16970878 VDDA 0.5 TC=0,0
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E_ABM23 N16671640 0 VALUE { IF( V(N16671552) > V(N16672106) , 5 , 0 )
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+ }
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R_R10 GND INB 50k TC=0,0
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V_V10 N16670888 0 5.5
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C_C44 0 N17407797 1.443n
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X_S6 N17167706 0 N17167704 VSSB UCC21220AD_TRANS_S6
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R_R5 0 INB_OK 1K TC=0,0
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R_R57 VCCI_1 VCCI_0 1m TC=0,0
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X_U43 UVLOB FAULT_INP N16669858 AND2_BASIC_GEN PARAMS: VDD=5 VSS=0
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+ VTHRESH=2.5
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E_ABM27 DRVA_PASS 0 VALUE { IF( V(N16671468)>2.5 &
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+ +V(N17396123) < 2.5, 5, 0) }
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V_V7 N16673432 0 1.8
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R_R28 DISABLE GND 100k TC=0,0
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V_V9 N16672106 0 1
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V_V5 N16670154 0 2
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X_U33 OUTA VDDA D_D1
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R_R54 N17198437 UVLOB 1 TC=0,0
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C_C39 VSSA N17127259 110p
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C_C42 0 N17198437 1n
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E_E20 INB_INT 0 INB GND 1
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T_T2 INB_PRE 0 INB_OK 0 Z0=1K TD=22n
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I_IQuiescentB VDDB VSSB DC 1.2m
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E_E6 N16672784 OUTB VALUE { if ( V(DRVB, 0) >2.5, 12 , 0 ) }
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V_V8 N16671580 0 2
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R_R29 N16671166 N16671236 1 TC=0,0
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C_C24 0 N16672528 1.443n
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X_U54 DIS N16698404 INV_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5
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V_V6 N16670672 0 1
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E_E11 N16670896 N16670888 N17198437 0 {-0.3/5}
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E_E7 N16669580 0 INA_OK 0 1
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X_U61 DRVA N17153666 INV_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5
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C_C31 0 N16671830 1.443n
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E_ABM1 UVLO1 0 VALUE { if ( V(VCCI_INT) > V(N16669842), 5 , 0 ) }
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R_R33 N16673116 N16673790 5 TC=0,0
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C_C30 0 N16670162 1.443n
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E_ABM28 DRVB_PASS 0 VALUE { IF( V(N16671702)>2.5 &
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+ +V(N17407797) < 2.5, 5, 0) }
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R_R38 0 N16669674 1k TC=0,0
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C_C27 0 N16673790 1.443N
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X_H1 N16670816 VCCI_0 DEAD_THRESH 0 UCC21220AD_TRANS_H1
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X_M14 N16672776 N16672784 OUTB HIGHMOS
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E_ABM26 N16670408 0 VALUE { IF( V(INB_OKD)<2.5 &
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+ +V(N16670162) >2.5, 5, 0 ) }
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C_C41 0 N17196585 1n
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R_R52 N17110021 N17110019 3.3 TC=0,0
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E_E10 N16673418 N16673354 N16673116 0 {-0.8}
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R_R37 INA_OKD N16671830 3.5 TC=0,0
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G_ABM2I1 N16670154 N16670120 VALUE { IF(V(INB_OKD) < 2.5 ,
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+ If(V(DEAD_THRESH)< 5u, 0.35, LIMIT((V(DEAD_THRESH)*100/V(VCCI_INT)), 0.35,0)),
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+ 0) }
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R_R34 N16670228 N16671468 1 TC=0,0
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.ENDS UCC21220AD_TRANS
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*$
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.subckt UCC21220AD_TRANS_S4 1 2 3 4
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S_S4 3 4 1 2 _S4
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RS_S4 1 2 1G
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.MODEL _S4 VSWITCH Roff=1e6 Ron=5m Voff=0.5V Von=4.5V
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222 |
.ends UCC21220AD_TRANS_S4
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*$
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.subckt UCC21220AD_TRANS_S2 1 2 3 4
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S_S2 3 4 1 2 _S2
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RS_S2 1 2 1G
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.MODEL _S2 VSWITCH Roff=1e9 Ron=10m Voff=1 Von=4
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.ends UCC21220AD_TRANS_S2
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*$
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.subckt UCC21220AD_TRANS_S1 1 2 3 4
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S_S1 3 4 1 2 _S1
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RS_S1 1 2 1G
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.MODEL _S1 VSWITCH Roff=1e9 Ron=10m Voff=1 Von=4
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.ends UCC21220AD_TRANS_S1
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*$
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.subckt UCC21220AD_TRANS_S3 1 2 3 4
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S_S3 3 4 1 2 _S3
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RS_S3 1 2 1G
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.MODEL _S3 VSWITCH Roff=1e6 Ron=25 Voff=0.5V Von=4.5V
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.ends UCC21220AD_TRANS_S3
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*$
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.subckt UCC21220AD_TRANS_S5 1 2 3 4
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S_S5 3 4 1 2 _S5
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RS_S5 1 2 1G
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.MODEL _S5 VSWITCH Roff=1e6 Ron=25 Voff=0.5V Von=4.5V
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.ends UCC21220AD_TRANS_S5
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*$
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.subckt UCC21220AD_TRANS_S6 1 2 3 4
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S_S6 3 4 1 2 _S6
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RS_S6 1 2 1G
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.MODEL _S6 VSWITCH Roff=1e6 Ron=5m Voff=0.5V Von=4.5V
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.ends UCC21220AD_TRANS_S6
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*$
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254 |
.subckt UCC21220AD_TRANS_H1 1 2 3 4
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H_H1 3 4 VH_H1 1
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VH_H1 1 2 0V
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257 |
.ends UCC21220AD_TRANS_H1
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258 |
** Wrapper definitions for AA legacy support **
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259 |
*$
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260 |
.subckt d_d1 1 2
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261 |
d1 1 2 dd
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262 |
.model dd d
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263 |
+ n=0.001
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264 |
.ends d_d1
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265 |
*$
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266 |
.subckt lowmos d g s
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267 |
m1 d g s s _mod
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268 |
.model _mod nmos
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269 |
+ kp=2e-009
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270 |
+ w=2.4
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271 |
+ l=1e-008
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272 |
+ vto=0
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273 |
+ n=2.5
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274 |
+ rg=0
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275 |
+ cgso=0
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276 |
.ends lowmos
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277 |
*$
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278 |
.subckt highmos d g s
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279 |
m1 d g s s _mod
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280 |
.model _mod nmos
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281 |
+ kp=2e-009
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282 |
+ w=0.285
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283 |
+ l=1e-008
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284 |
+ vto=0
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285 |
+ n=2.5
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286 |
.ends highmos
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287 |
*$
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288 |
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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289 |
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} &
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290 |
+ V(B) > {VTHRESH},{VDD},{VSS})}}
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291 |
RINT YINT Y 1
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292 |
CINT Y 0 1n
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293 |
.ENDS AND2_BASIC_GEN
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294 |
*$
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295 |
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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296 |
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} |
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297 |
+ V(B) > {VTHRESH},{VDD},{VSS})}}
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298 |
RINT YINT Y 1
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299 |
CINT Y 0 1n
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300 |
.ENDS OR2_BASIC_GEN
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301 |
*$
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302 |
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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303 |
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
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304 |
+ {VSS},{VDD})}}
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305 |
RINT YINT Y 1
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306 |
CINT Y 0 1n
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307 |
.ENDS INV_BASIC_GEN
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308 |
*$
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