Subversion Repositories Electronics.Rangefider

Rev

Rev 1 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
1 florent_ba 1
* PSpice Model Editor - Version 16.2.0
2
*$
3
* LM5114A
4
*****************************************************************************
5
*  (C) Copyright 2013 Texas Instruments Incorporated. All rights reserved.
6
*****************************************************************************
7
** This model is designed as an aid for customers of Texas Instruments.
8
** TI and its licensors and suppliers make no warranties, either expressed
9
** or implied, with respect to this model, including the warranties of 
10
** merchantability or fitness for a particular purpose.  The model is
11
** provided solely on an "as is" basis.  The entire risk as to its quality
12
** and performance is with the customer
13
*****************************************************************************
14
*
15
** Released by: WEBENCH Design Center, Texas Instruments Inc.
16
* Part: LM5114A
17
* Date: 18FEB2013
18
* Model Type: TRANSIENT
19
* Simulator: PSPICE 
20
* Simulator Version: 16.2.0.p001
21
* EVM Order Number: LM5114 EVAL BOARD
22
* EVM Users Guide: SNVA625–January 2012
23
* Datasheet: SNVS790D–JANUARY 2012–REVISED AUGUST 2012
24
*
25
* Model Version: Final 1.00
26
*
27
*****************************************************************************
28
* Updates:
29
*
30
* Final 1.00
31
* Release to Web.
32
*****************************************************************************
33
.SUBCKT LM5114A  IN INB  VDD P_OUT N_OUT VSS
34
V_V2         N16505370 VSS 3.8
35
E_ABM4         N16515305 0 VALUE { 0.34*V(VDD)    }
36
X_U3         INB N16505719 N16515305 N16504880 COMPHYS_BASIC_GEN PARAMS: VDD=1
37
+  VSS=0 VTHRESH=0.5
38
E_ABM3         N16505719 0 VALUE { 0.67*V(VDD)    }
39
X_U5         UVLO N14509334 N3 N16510505 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0
40
+  VTHRESH=500E-3
41
X_U1         VDD N16505370 N165112383 UVLO COMPHYS_BASIC_GEN PARAMS: VDD=1
42
+  VSS=0 VTHRESH=0.5
43
X_S1    N14508796 VSS VDD P_OUT LM5114A_S1 
44
T_T1         N16510505 VSS N16508556 VSS Z0=1000 TD=10n  
45
E_ABM1         N16505537 0 VALUE { 0.67*V(VDD)    }
46
X_U2         IN N16505537 N16514778 N14509334 COMPHYS_BASIC_GEN PARAMS: VDD=1
47
+  VSS=0 VTHRESH=0.5
48
X_U4         N16504880 N3 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
49
R_R1         VSS N16508556  1k TC=0,0 
50
V_V1         N165112383 VSS 0.4
51
X_S2    N14508796 VSS N_OUT VSS LM5114A_S2 
52
E_ABM2         N16514778 0 VALUE { 0.34*V(VDD)    }
53
X_U6         N16508556 N14508796 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
54
+  VTHRESH=500E-3
55
.ENDS LM5114A
56
*$
57
.SUBCKT LM5114A_S1 1 2 3 4  
58
S_S1         3 4 1 2 _S1
59
RS_S1         1 2 1G
60
.MODEL         _S1 VSWITCH Roff=1e6 Ron=3.85 Voff=0.6 Von=0.4
61
.ENDS LM5114A_S1
62
*$
63
.SUBCKT LM5114A_S2 1 2 3 4  
64
S_S2         3 4 1 2 _S2
65
RS_S2         1 2 1G
66
.MODEL         _S2 VSWITCH Roff=1e6 Ron=0.66 Voff=0.4 Von=0.6
67
.ENDS LM5114A_S2
68
*$
69
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
70
EIN INP1 INM1 INP INM 1 
71
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
72
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
73
R1 OUT 1 1
74
C1 1 0 5n
75
RINP1 INP1 0 1K
76
.ENDS COMPHYS_BASIC_GEN
77
*$
78
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
79
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
80
+ V(B) > {VTHRESH} &
81
+ V(C) > {VTHRESH},{VDD},{VSS})}}
82
RINT YINT Y 1
83
CINT Y 0 1n
84
.ENDS AND3_BASIC_GEN
85
*$
86
.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
87
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
88
+ {VSS},{VDD})}}
89
RINT YINT Y 1
90
CINT Y 0 1n
91
.ENDS INV_BASIC_GEN
92
*$
93
.SUBCKT POWERMOS G D S PARAMS: RDSON=16m Ciss=1375p Crss=70p Coss=340p VSP=3.5 RG=1
94
* This is a simple model for Power MOSFET.
95
* The parameters modeled are
96
* - RDSon,
97
* - Input Capacitance,
98
* - Reverse capacitance,
99
* - Output capacitance,
100
* - Switching point voltage (Gate voltage where the FET starts switching),
101
* - Gate Resistance
102
C_C1         S Da  {Coss} IC=0
103
R_R1         Da D  10
104
C_C2         Ga D  {Crss}  IC=0
105
R_R2         G Ga {RG}
106
C_C3         Ga S  {Ciss} IC=0
107
D_D1         S Db Dbreak
108
R_R3         Db D 1m
109
S_switchM         D S Ga S _switchM
110
RS_switchM         Ga S 100Meg
111
.MODEL         _switchM VSWITCH Roff=100e6 Ron={RDSON} Voff=1.1 Von={VSP}
112
.model Dbreak D Is=1e-14 Cjo=.1pF Rs=.01
113
.ENDS POWERMOS
114
*$
115
.MODEL DIODE D
116
+ RS=.5
117
+ CJO=100.00E-15
118
+ M=.3333
119
+ VJ=.75
120
+ ISR=100.00E-12
121
+ BV=100
122
+ IBV=100.00E-6
123
+ TT=5.0000E-9
124
*$